The present invention relates to a timer circuit and, more particularly, to a timer circuit provided as one of peripheral units of a microcomputer.
A microcomputer includes various types of peripheral units. A timer circuit is one of the peripheral units. The timer circuit counts a clock signal to issue cyclically an interrupt request to a central processing unit (CPU) of the microcomputer. The CPU suspends the program execution in response to the interrupt request and initiates an interrupt program. The cycle of the interrupt request can be set by the CPU.
More specifically, as a timer circuit according to prior art is shown in FIG. 6, the CPU (not shown}generates a read-enable signal WENS while supplying a register 60 with data indicative of the cycle period, count data DIN. In response to the signal WENS, the register 60 fetches and supplies the data DIN to a comparator 61. On the other hand, a counter 62 is counting a clock signal having a reference cycle and reset by the signal WENS through an OR gate 63. The counter 62 resumes the clock counting operation when the write-enable signal WENS disappears. The count value of the counter 62 is supplied to the comparator 61. Therefore, when the count value of the counter 62 reaches the data stored in the register 60, the comparator 61 produces an interrupt request signal INTQ. This signal INTQ resets the counter 62 through the OR gate 63. The counter thereafter resumes the clock counting operation. The cycle period of the interrupt request signal INTQ is thus controllable by the value of the count data DIN.
Although the write operation of the count data DIN into the register 60 is performed by the instruction execution by the CPU, the write-enable signal WENS happens to be produced undesirably due to the variation in a power voltage or an external noise. In this case, the counter 62 is reset to an initial value, and the register 60 fetches the count data DIN of this time. If the content of the count data DIN of this time is equal to the initial value of the counter 62, the comparator produces immediately the interrupt request signal INTQ. The CPU is shifted to execute the interrupt program. The interrupt request signal INTQ resets the counter 62 to the initial value, whereas the register 60 retains the data equal to the initial value of the counter 62. For this reason, the comparator 61 is brought into a condition of continuing to produce the interrupt request signal INTQ. The CPU is thus never released from the interrupt program routine. Such an abnormal condition may occur by a programming miss in which the content of count data to be written into the register 60 by the execution of a data write instruction is the same as the initial value of the counter 62.